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jch4416's avatar
jch4416
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Quartus doesn't recognize clocks generated by division of the same master clock as synchronous

Hello, I am working on a rather slow (1.8432MHz master clock) cpld design. There are 4 clocks that I generate by dividing the master clock by different integers. The divisions are done with synchro...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

KhaiY