Quartus doesn't recognize clocks generated by division of the same master clock as synchronous

Thanks for your reply. I am working with the MAX II family, an EPM570 cpld, and coding in Verilog.

Here is the error message:

Critical Warning (308060): (High) Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains. (Value defined:2). Found 17 asynchronous clock domain interface structure(s) related to this rule.

I have my clocks defined in the sdc file as shown below. All are integer divisions of the same master and the dividers are synchronous counters. I changed the divisor on the last one just for the constraint because Quartus can't seem to deal with very slow clocks

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create_clock -name {cpld_master_clock} -period 542.000 -waveform { 0.000 271.000 } [get_nets {cpld_master_clock}]

#**************************************************************
# Create Generated Clock
#**************************************************************

create_generated_clock -name {uart_rx_clock} -source [get_nets {cpld_master_clock}] -divide_by 2 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV2|clk_out}]
create_generated_clock -name {uart_tx_clock} -source [get_nets {cpld_master_clock}] -divide_by 32 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV3|clk_out}]
create_generated_clock -name {millisec_clock} -source [get_nets {cpld_master_clock}] -divide_by 1920 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV4|clk_out}]
create_generated_clock -name {heartbeat_clock} -source [get_nets {cpld_master_clock}] -divide_by 3840 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV5|clk_out}]