Quartus doesn't recognize clocks generated by division of the same master clock as synchronous

Hi,

The potential cause of this warning could be either

Cause #1: In the current design, the Design Assistant found the specified number of structures where single-bit data is transferred between asynchronous clock domains, but none of the data bits are synchronized. To reduce metastability problems, each data bit should be synchronized with two or more cascading registers in the receiving asynchronous clock domain. The submessage(s) of this message list the structure(s) that the Design Assistant found.

>> Synchronize all the data bits.

Cause #2: In the current design, the Design Assistant found the specified number of structures where multiple-bit data is transferred between asynchronous clock domains, but none of the data bits are synchronized. To reduce metastability problems, the data bits that act as REQ (Request) and/or ACK (Acknowledge) signals for the transfer should be synchronized with two or more cascading registers in the receiving asynchronous clock domain. The submessage(s) of this message list the structure(s) that the Design Assistant found.

>> Synchronize the data bits that act as REQ and/or ACK signals.

Thanks

Best regards,

KhaiY