Forum Discussion
New ContributorQuartus 20.1 and warnings about Latches
Hi,
still some misunderstandings in your latest post.
First point, you don't need to worry about possible latch generation in clocked processes, neither about additional sensitivity list entries.
The LEs you have marked in technology map viewer are not part of combinational pathes. All logic pathes start and end at a DFF (or an IO pin).
The key observation is that bits SpeedLimit(4 downto 0) which are claimed as latches by Quartus don't exist in the design at all. The respective output bits are tied to ground. This happens because SpeedLimit is varied in steps of 100000, which can be factorized as 2^5*5^5. Factor 2^5 corresponds to 5 LSB staying zero. Changing the limits (your first experiment) allows more steps but keeps step size 100000.
If you change one step to e.g. 100001, register bits SpeedLimit(4 downto 0) are implemented and the latch warning disappears.
It has been also suggested to change the reset to synchronous to remove the warning, I already rated the suggestion as inappropriate.
Why?
1. It's unnecessary. It masks an erroneous warning but doesn't solve a real issue.
2. It increases resource utilization, e.g. 27 to 35 LE with Cyclone 10 LP implementation. Asynchronous reset is already implemented in registers and "free" in terms of logic resources if you use a global reset signal, synchronous reset need additional logic.
3. It may have other unwanted effects, depending on the reset scheme of your application.
As stated, the warning is erroneous and should be corrected by Intel. For the time being, you can disable the warning by a synthesis directive in front of the architecture declaration
-- altera message_off 10631
-- altera message_off 10041
Best regards
Frank
New ContributorThank you all for your collaboration.
Let's see if I'm able to explain the tests I made after reading your hints, because this stuff is more dense than I expect:
First, using the hint of @FvM I change the code, eliminating the line with the sentence SpeedLim <= SpeedLim; and change one limit value for some value which is 2^n - 1 (all ones in the value), and the result was the following:
In this situation the warning appear again and the logic synthetized has in fact some latchs (at least combinatorial logic) around the SpeedLimit, we can see those in the Map Viewer, like this:
Next, I replace the increment of the signal SpeedLimit to some value which is also a power of 2 minus 1.
In this situation, all the warnings disappear and all the logic around SpeedLimit is edge triggered, see the following images:
In the Map Viewer I didn't found any combinational logic around SpeedLimt:
The first conclusion is that the Latchs stuff are dependent (at least) of the values that the variable takes, I mean, the use of the bits that represent the variable.
Next, related with the suggestion of @ShengN_Intel , I changed the process like you told, and the result is:
The warning disappear, but there are combinatorial logic around SpeedLimit. I don´t know if that logic has a chance to create Latchs problems or not:
I think there are no need to paste more pictures, anyway if I use the same change that I made in the test above, I mean, use a power of 2 minus 1 to increment the SpeedLimit, all the logic associated to this signal will be also edge triggered.
Second conclusion, the Sync or Assync use of reset has influence in the warnings related with the Latchs stuff. Anyway, there are som combinatorial logic around SpeedLimt signal (and is not the use of the signal, it is the generation of the signal itself, at least, this is my interpretation)
Related to the suggestion of @sstrell , the signal SpeedLimt was in the sensitivity list because my first change was to insert the useless statement SpeedLimit <= SpeedLimit inside the process, and when I did this, I got one warning related with the use of the signal inside the process and wasn't in the sensitivity list. In a curious way I can't repeat this.
So, for the future, I looks like Quartus has some reasons to give warnings, but not always in a clear way.
This stuff is completely new for me and I think that I need to learn to live with the warnings ...
Thanks again for your collaboration.
