Quartus 18.0 generates a different RBF file for each compile. What setting is causing this behavior? Please see details section

How is the .rbf file different? Any time the Assembler runs during a full compilation, it will generate a new programming file. You can choose to not run the Assembler automatically during a full compilation in the compiler settings.

#iwork4intel

I diffed the two .rbf files with the tool KDiff3 and they were not binary equivalents. I have two other FPGA projects compiled with Quartus 18.0 multiple times and the output .rbf files were always identical. What is the function of the Assembler?

Hi,

Assembler generates programming & configuration files in Quartus tool.

whenever you compile the design in Quartus tool, the assembler automatically generates the programming files. It also allows to convert configuration files to programming files for configuration devices.

Have to checked the previous post about Assembler(uncheck) option during compilation?

Refer the screenshot & try to compare again.

Assignments -> Settings..

please let me know, how it woks for you.

Regards,

Vicky

Thanks for the reply. I understand that the Assembler generates all the programming files and can be turned off during compilation, but that does not address my original concern where the output of the compilation (RBF file) is different for each iteration. We should get the exact same output every time we compile since the input source files and compile settings are the same. Could you please review that attached QAR file and investigate what is the root cause for this issue? Thanks.

Hi,

Apologies for the late response.

I tried to compare(Using Non Intel KDiff3 Tool, which we can`t give surety) the .rbf files generated from project provided in very first post & I observed that, there is conflict. I also realized the same behavior for two different projects which consist of one or more IPs used in design but, when I tried to compare .rbf file generated after multiple time of compilation of a project(which doesn`t consist of IP/IPs in design), got result identical .rbf files so I am not sure the exact reason but observation is that the design which consists of IPs differs while compilation.

Regards,

Vicky

Hi,

Could you provide that similar FPGA design for comparison purpose?

check another design which should have IPs but excluding PLL, you can also check with different edition & version of Quartus

Thanks,

Vicky

Hi,

Thanks for the design.

I checked with your design & observed that .rbf files generated from this project shows equivalent by KDiff3 Tool even this project consists of PLL IP. so as you mentioned in your very first post , there might be some issue with that design.

let me check with my team since issue is replicated & get back to you.

Regards,

Vicky

Hi Phil,

This case got escalated to me at this point. I will contact you via email for further clarifications.

Thanks,

Joseph

Hi Phil,

Please contact your distributor as we've got internal ticket resolved for this. They will provide further clarification in details.

Thanks,

Joseph