Forum Discussion
Hi,
Thanks for the design.
I checked with your design & observed that .rbf files generated from this project shows equivalent by KDiff3 Tool even this project consists of PLL IP. so as you mentioned in your very first post , there might be some issue with that design.
let me check with my team since issue is replicated & get back to you.
Regards,
Vicky
- PFong26 years ago
New Contributor
Please double check the compiler settings between the two QAR files as well to ensure that it's not any compiler setting causing the issue. Thanks.
- SZack6 years ago
Occasional Contributor
Hi Vicky,
I am the Intel PSG FAE at Arrow that supports this customer and I could replicate the issue also but could not explain why this issue was happening. I looked at the "good" design to check the settings and didn't see anything different from the "bad" design.
Have you or your team had a chance to investigate why this one design from the customer gets different RBF files after each compile?
Steve Zack
- Vicky16 years ago
Regular Contributor
Hi PFong2 & SZack,
Could you please check again by creating the fresh deign with all the files included in that erroneous design?
we are working on it & will let you know once we get any update.
Thanks,
Vicky
- PFong26 years ago
New Contributor
Hi Vicky,
We have two designs that use the similar core modules that do not exhibit this issue. Only the initial design (SRM_VENTNOR) that I sent you has this issue. It's been over two months since I submitted this inquiry. Could we escalate this issue so we can converge on a resolution sooner than later?
Thanks,
Phil