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PFong2's avatar
PFong2
Icon for New Contributor rankNew Contributor
6 years ago

Quartus 18.0 generates a different RBF file for each compile. What setting is causing this behavior? Please see details section

I have attached a qar file that was archived with Quartus 18.0. When we restored this project and compiled, we got a different RBF file than the original SRM_VENTNOR.rbf file that is attached. Each t...
Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Could you provide that similar FPGA design for comparison purpose?

check another design which should have IPs but excluding PLL, you can also check with different edition & version of Quartus

Thanks,

Vicky

PFong2's avatar
PFong2
Icon for New Contributor rankNew Contributor
6 years ago

I've uploaded the similar FPGA design (SRM_5000.qar) along with the output RBF file (SRM_5000.rbf). You will need to extract the SRM_5000.rbf file from the SRM_5000_RBF zip file.

Please restore this design and compile twice. A comparison of the two output RBF files will show that they are binary equivalents. Please investigate root cause of this issue. Thanks.

  • PFong2's avatar
    PFong2
    Icon for New Contributor rankNew Contributor
    6 years ago

    I attached it again. Please confirm you can download the SRM_5000.qar file.

  • Vicky1's avatar
    Vicky1
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Please attach the SRM_5000.qar file.

    Regards,

    Vicky