Forum Discussion
Honored ContributorQsys
As you find workarounds to Qsys issues please add them to the list found here: http://www.alterawiki.com/wiki/new_qsys_issues
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Altera_ForumDoes the set change occur anywhere in the middle of the 128 entry pattern or just when the counter rolls over? If it can happen at any time do you reset the counter or just continue where you left off?
I'm picturing a memory that contains two or more sets of data and a master that knows how to jump between sets. If at the time of a set change you have to flush out any data already preloaded from the old set then that would introduce gaps in your output. So if you clocked the master and memory higher than the rate that ALTGX consumes this data then I could see this being achieved using a clock crossing FIFO (at the expense of even more latency). If you are allowed to let an element or two through from the old set on a set change then this switchover should be fairly trivial. Also using a dual port memory might allow you to be reading two sets in parallel so that you can switch over easier.- Altera_Forum
In my application (which is not a communication of data) it is critical that that upon a switch of data bit sets the current bit position of the serializer is maintained - it simply sends out the same position bit value form the new data bit set. The set switch is synchronous with the clock but not with the serializer.
In theory, the correct implementation of the function that I need is with a MUX 128:1 and a free running 7 bit counter that cyclically addresses the MUX at the output clock rate. In this way a change in the data at the input of the MUX changes the output stream immediately - as in the next bit state. I am forced to use the ALTGX IP which includes a FIFO to get access to the GX serial output and that messes up my output stream.... Moreover there are some 10 - 32 sets of bits and the selection of sets is done in hardware by controlling the set address through I/O pins. but for now - proof of concept - I can live with the FIFO provided nothing is reset when a set is switched. The result would be a delay in the duration that it would take bits from the new set to show up in the output but the bit position in the set would be kept. since neither the data word counter or the FIFO sequence are disturbed. - Altera_Forum--- Quote Start --- The byteblaster issue is a bit annoying but at the moment I've resolve it as suggested on the websites. --- Quote End --- which problem is this? I've been having issues with my computer bluescreening upon connecting to byteblaster and have had no luck finding any solutions to this.
- Altera_Forum
Ok, I'm reverting back to QII v9.0 and SOPC Builder and Nios2-studio because they all worked. The SDI Audio extract and embed are not worth it, Qsys is extremely slow to generate, and randomly works or doesn't, and Nios2 Eclipse build tools can't remember your Flash programming settings from one minute to the next (though apparently, if you create an empty flash settings file, and save to that, then it will work, but not the handy list of projects you got with nios2-studio).
Also the VHDL editor in QII 11.0sp1 is a retro-grade step from QII 9.0. The gripes I've got so far may not sound much but make some things much more laborious: 1) Column block editing is broken. You can select, and cut and delete column blocks, but pasting fails completely - it doesn't think you want your pasted block inserted as a column on the lines that are already there, and instead pastes them into new lines. Ha ha ha 2) You can't get a split screen in the editor anymore, so comparing your component declaration to the instantiation is a pain in the a**e. Qsys: 1) The tristate bus problems seem to be well documented here: http://www.alteraforum.com/forum/showthread.php?p=119780#post119780 (http://www.alteraforum.com/forum/showthread.php?p=119780#post119780) but since then I've compiled my design, which after that thread had programmed flash beautifully, and not having changed ANYTHING in Qsys, only to find that the flash programmer can erase my flash, and program the first 120 bytes or so, but then gives up. This is on a board that I've compiled and recompiled multiple (at least 20 different) designs for in QII v9.0 and SOPC Builder and NEVER EVER had that happen. 2) Qsys seems to take an AGE to generate. I assume it's all the inserting Merlin stuff between all the avalon components, etc. But I suspect they introduce timing problems with my flash programming as well, so are not worth it. 3) All the memories I had generated for v9.0 don't seem to work, and there doesn't seem to be any way of adding a "this is a memory" tag to a custom component. Fortunately the memory generator in Qsys seems to let you generate internal memory relatively quickly, though you get many more signals than you used to in v9.0 All in all, not a happy chap.:( - Altera_Forum
Hi.
Did anyone try to use AXI interface in Qsys 11.1? It's supposed to be supported there. I was expecting to see AXI interface on NIOS processor, but Only Avalon interfaces exist. How can an IP with AXI slave interface be connected to NIOS? Should the protocol conversion from Avalon to AXI be performed by means of some Altera IPs? In addition, In Components library of Qsys under Qsys Interconnect there's "AXI Interface" section with 2 components : AXI Master Network Interface and AXI Slave Network Interface. AXI Slave Network Interface accepts command packets on avalon_streaming interface and issues the resulting transactions to the AXI interface. 1) Does it mean that for connecting AXI IP to NIOS we should first translate Avalon-MM interface of NIOS to Avalon-ST interface, and after that use AXI Slave Network Interface? 2) There's no any documentation on AXI Master and Slave blocks. There're a lot of parameters inside and it's unclear how to set them. Does anyone have a clue how to deal with it? - Altera_Forum
Since I already answered you in the other thread you created I won't repeat myself. Others inquiring about AXI support should read this: http://www.alterawiki.com/wiki/axi_support Note that AXI support is beta in 11.1 so expect some pointy edges.
- Altera_Forum--- Quote Start --- Others inquiring about AXI support should read this: http://www.alterawiki.com/wiki/axi_support Note that AXI support is beta in 11.1 so expect some pointy edges. --- Quote End --- I'm not afraid to bleed ... :) There's an inconsistency in the release notes though: http://www.altera.com/products/software/quartus-ii/whats-new/swf-qts-whats-new.html Which states there is an "AXI® bus functional model (BFM) beta". whereas the Wiki states "There are no AXI bus functional models (BFMs) provided in this version". I'll download v11.1 and see which comment is true ... unless of course you know the answer off-hand ... Cheers, Dave
- Altera_Forum
It is somewhere in the middle. The HPS (hard processor system) has BFMs for the AXI ports on it but there are no standalone AXI BFMs yet. The HPS BFMs are not publicly documented yet so I don't think you will get very far trying to use them.
- Altera_Forum--- Quote Start --- It is somewhere in the middle. The HPS (hard processor system) has BFMs for the AXI ports on it but there are no standalone AXI BFMs yet. The HPS BFMs are not publicly documented yet so I don't think you will get very far trying to use them. --- Quote End --- Ok, I'll just take a cursory glance at them then. Cheers, Dave
- Altera_Forum
You'll want to look at the AXI bridge interfaces, the multi-port SDRAM controller AXI/Avalon interfaces do not have BFMs hooked up yet. The AXI bridge interfaces are the ones that support 32/64/128 bit data widths into the FPGA fabric.
