Qsys

Does the set change occur anywhere in the middle of the 128 entry pattern or just when the counter rolls over? If it can happen at any time do you reset the counter or just continue where you left off?

I'm picturing a memory that contains two or more sets of data and a master that knows how to jump between sets. If at the time of a set change you have to flush out any data already preloaded from the old set then that would introduce gaps in your output. So if you clocked the master and memory higher than the rate that ALTGX consumes this data then I could see this being achieved using a clock crossing FIFO (at the expense of even more latency). If you are allowed to let an element or two through from the old set on a set change then this switchover should be fairly trivial. Also using a dual port memory might allow you to be reading two sets in parallel so that you can switch over easier.