Qsys

In my application (which is not a communication of data) it is critical that that upon a switch of data bit sets the current bit position of the serializer is maintained - it simply sends out the same position bit value form the new data bit set. The set switch is synchronous with the clock but not with the serializer.

In theory, the correct implementation of the function that I need is with a MUX 128:1 and a free running 7 bit counter that cyclically addresses the MUX at the output clock rate. In this way a change in the data at the input of the MUX changes the output stream immediately - as in the next bit state.

I am forced to use the ALTGX IP which includes a FIFO to get access to the GX serial output and that messes up my output stream....

Moreover there are some 10 - 32 sets of bits and the selection of sets is done in hardware by controlling the set address through I/O pins.

but for now - proof of concept - I can live with the FIFO provided nothing is reset when a set is switched. The result would be a delay in the duration that it would take bits from the new set to show up in the output but the bit position in the set would be kept. since neither the data word counter or the FIFO sequence are disturbed.