Occasional ContributorQSYS 25.3pro failed to generate VHDL simulation files for altera_remote_update_core
Hello,
If I use altera_remote_update_core in a QSYS project using Quartus Version 25.3pro, the IP Generation fails with the following error message
Info: sib_flash_subsys_remote_update_0: "Generating: altera_remote_update_core"
Error: invalid command name "else"
Info: while executing
Info: "else {
Info: do_vhdl_sim_cbx altera_remote_update_core
Info: }"
Info: (procedure "do_vhdl_sim" line 8)
Info: invoked from within
Info: "do_vhdl_sim altera_remote_update_core"
Error: Generation stopped, 1 or more modules remaining
Despite the error message being not very meaningful, I realized, that this fails only, when I select Simulation Model "VHDL". If I select simulation model "none" or "verilog" IP Generation works fine.
The error is reproduceable by a simple QSYS project, which only contains altera_remote_update IP core.
The error only occurs in Quartus 25.3pro. Using the exactly same project with Quartus 24.1pro works without error.
Please advice, I would appreciate any help on this topic.
Thanks
best regards
Fabian
Thank you for finding this issue.
I was able to duplicate the error and will ask our tool specialist to further investigate.
In the meantime, as a workaround, please avoid selecting "VHDL" for Simulation Model generation.
Regards,
Richard Tan
