Python and VHDL

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I have a component in VHDL and I wanna making several copy of it and creating a Mesh M*N dimensions with them, if I will define whole the signals between them its take a long times in VHDL because I have to define more than 2000 signals between them and I think its not proper method but I think so I can using the Python to taking instance of them and finally export again to VHDL file. it is mean I using the Python only to definition and communication different signals between several component deposit this component before wrote by VHDL. if it is possible please tell me how can i using the python for do that.

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You do not need to use Python. You can use VHDL and a generate loop. If the signal indexing is complicated, then you can also use a VHDL function.

Look at the pipelined mux figure and code posted in this thread:

http://www.alteraforum.com/forum/showthread.php?t=41601

and you'll see examples of how to use generate statements.

You can also look at the code for this LFSR/PRBS tutorial

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip

and in lfsr_tutorial_src\prbs\src\prbs.vhd you'll see how functions can be used to make complicated VHDL easier to read.

Cheers,

Dave

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Yes it is true I can generated it by function or for generate loop in VHDL, but I wanna learned how can I using of the Python script language in VHDL files. and this communication between the VHDL files and Python how is it?

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There is no communication.

If you want to use Python to create VHDL, then you would simply use Python to create VHDL files.

If you want to have the Python create the files based on VHDL generics provided in the Quartus GUI, then you will have to use a Tcl pre-flow script to run the Python code.

My advice is that if VHDL can generate the logic you need, then use VHDL. You are overly complicating things if you need to use Python in your scripting flow. If you have to use scripts, then stick with Tcl, and your scripts will then be portable to other users. No-one on this forum will be interested in helping you debug your Python, but you will get help debugging VHDL and Tcl.

Cheers,

Dave

Well, I for one am interested in Python and, specifically, MyHDL as it applies to this use case. I would certainly provide help along these lines...

Certainly, coding in Python (or other HLS option) is more interesting than sticking with the staid and rather boring...not to mention _ancient_ (nearly 30 years old!) design paradigm that is coding in Verilog/VHDL/SystemVerilog. :-)

Cheers!

slacker

You do that if you want.

Good luck getting it to work with anything other than MyHDL.

Also, it is of not use in the job market.

MyHDL just produces VHDL or Verilog.

In my experience, all tools that auto-generate HDL for you tend to be rubbish.

PS. System Verilog was only standardised in 2005.

Hi Slacker,

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Well, I for one am interested in Python and, specifically, MyHDL as it applies to this use case. I would certainly provide help along these lines...

Certainly, coding in Python (or other HLS option) is more interesting than sticking with the staid and rather boring...not to mention _ancient_ (nearly 30 years old!) design paradigm that is coding in Verilog/VHDL/SystemVerilog. :-)

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The practical reality of designing with FPGAs is that you are "stuck" with using whatever language that the vendor supports. I first selected VHDL because MAX+PLUS II did not support various Verilog constructs. I'm not an expert SystemVerilog user, but it appears to have lots of modern object-oriented constructs ... alas, I see various threads on things that work in Modelsim, but do not work in Quartus.

By all means play with MyHDL, and run the designs through Quartus, there are lots of happy users of the tools. However, once you have spent the time learning an HDL language (ancient though they may be), you'll find that there's really no advantage in using MyHDL over performing similar language tricks in an HDL language.

Cheers,

Dave

Would be nice if those pontificating had actually tried said language/tool...fair enough?

MyHDL produces VHDL and Verilog that is quite usable/legible. Sure, it's not supported by a big name company (not sure that offers much value anyway), but the person developing it is by no means a noob to HDL/RTL or the industry as a whole.

It offers automated testbench generation in the end-simulator of your choice (including ModelSim) and works well with all of the freely available simulation tools (iVerilog, GHDL, GTKWave, etc.). Plus, it has the additional benefit of Python's great unit testing options.

Python's also becoming more and more the lingua franca in all sorts of fields.

To each his own, of course, but categorically shutting doors on things like this cannot possibly be good policy if progress and improvement are the end goal. Besides which, 30+ years of what is essentially the same design paradigm is not exactly what I would call progress. Yes, I think I can safely state that the IC design industry (interestingly, FPGA design still follows this paradigm as well...) has succeeded in spite of not because of the "advanced tools" that have been delivered by the EDA industry.

I don't want to start a flame war, but I think ideas should succeed and tools should be used on their own merit, not pre-conceived notions.

Cheers!

slacker

Hi Slacker,

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Would be nice if those pontificating had actually tried said language/tool...fair enough?

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It was not my intention to pontificate, I was merely explaining the situation of many of the users of these tools, i.e., we have selected the development languages of VHDL, Verilog, and Tcl, not by choice, but by default.

I did look at MyHDL in its earlier days, and did chat with some of the active developers at the Embedded Systems Conference in San Jose last year. Its a cool looking project and language.

However, since I am already familiar with VHDL and writing testbenches in VHDL, I have not found any incentive to change over to MyHDL (which you can read as "old and set in his ways" if you like).

Feel free to enlighten the curmudgeons amongst this group and write a tutorial showing how to create a reasonably complex system using MyHDL (eg., one that includes MegaCore IP), or fire some ideas back and forth about how people can get started using MyHDL. Perhaps start a new thread called "MyHDL" or "Introduction to MyHDL".

Cheers,

Dave

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To each his own, of course, but categorically shutting doors on things like this cannot possibly be good policy if progress and improvement are the end goal. Besides which, 30+ years of what is essentially the same design paradigm is not exactly what I would call progress. Yes, I think I can safely state that the IC design industry (interestingly, FPGA design still follows this paradigm as well...) has succeeded in spite of not because of the "advanced tools" that have been delivered by the EDA industry.

I don't want to start a flame war, but I think ideas should succeed and tools should be used on their own merit, not pre-conceived notions.

Cheers!

slacker

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The design endgame is not VHDL/verilog. Its gates and registers. HDLs are just a well established method to produce and suitably verify these. It has 30 years of momentum, and changing something like this is not easy. MyHDL may be an amazing tool, but without adoption, it will be useless to anyone with it on their CV, and if you're someone with extensive MyHDL experience up against someone who spent the same time in the "advance tools" of the EDA idustry, you're probably not getting that job.

I am a VHDL engineer, but I will admit if you want a job you really need to know SystemVerilog and UVM. Thats what makes you most employable. Companies generally dont invest in tools without a solid background, and those tools need to show some kind of performance or productivity improvement before major companies will even think about trying them out.

Although you would probably argue they are not the same, I have experience using Matlab HDL coder and HDL coder. The former likes to be sold as the "one stop solution" for algorithm -> FPGA development, they like to gloss over the part that its not quite that simple if you want a space and timing optimised solution. Plus its another tool you have to learn to use. HDL coder wraps itself around VHDL/Verilog, but it wants to do everything its way (again, another tool to use etc etc)

Remember, most engineers are not fluent in Python. So thats your first barrier. Its a second language they need to understand (as they will really need to understand the generated Verilog/VHDL). And that is another risk - any language that generates another language will always have some bugs somewhere! (why do people that design PCBs still insist on checking the entire generated netlist, and get it reviewed?)