Python and VHDL

Would be nice if those pontificating had actually tried said language/tool...fair enough?

MyHDL produces VHDL and Verilog that is quite usable/legible. Sure, it's not supported by a big name company (not sure that offers much value anyway), but the person developing it is by no means a noob to HDL/RTL or the industry as a whole.

It offers automated testbench generation in the end-simulator of your choice (including ModelSim) and works well with all of the freely available simulation tools (iVerilog, GHDL, GTKWave, etc.). Plus, it has the additional benefit of Python's great unit testing options.

Python's also becoming more and more the lingua franca in all sorts of fields.

To each his own, of course, but categorically shutting doors on things like this cannot possibly be good policy if progress and improvement are the end goal. Besides which, 30+ years of what is essentially the same design paradigm is not exactly what I would call progress. Yes, I think I can safely state that the IC design industry (interestingly, FPGA design still follows this paradigm as well...) has succeeded in spite of not because of the "advanced tools" that have been delivered by the EDA industry.

I don't want to start a flame war, but I think ideas should succeed and tools should be used on their own merit, not pre-conceived notions.

Cheers!

slacker