--- Quote Start ---
I have a component in VHDL and I wanna making several copy of it and creating a Mesh M*N dimensions with them, if I will define whole the signals between them its take a long times in VHDL because I have to define more than 2000 signals between them and I think its not proper method but I think so I can using the Python to taking instance of them and finally export again to VHDL file. it is mean I using the Python only to definition and communication different signals between several component deposit this component before wrote by VHDL. if it is possible please tell me how can i using the python for do that.
--- Quote End ---
You do not need to use Python. You can use VHDL and a generate loop. If the signal indexing is complicated, then you can also use a VHDL function.
Look at the pipelined mux figure and code posted in this thread:
http://www.alteraforum.com/forum/showthread.php?t=41601 and you'll see examples of how to use generate statements.
You can also look at the code for this LFSR/PRBS tutorial
http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip and in lfsr_tutorial_src\prbs\src\prbs.vhd you'll see how functions can be used to make complicated VHDL easier to read.
Cheers,
Dave
Honored Contributor
