Python and VHDL

Hi Slacker,

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Well, I for one am interested in Python and, specifically, MyHDL as it applies to this use case. I would certainly provide help along these lines...

Certainly, coding in Python (or other HLS option) is more interesting than sticking with the staid and rather boring...not to mention _ancient_ (nearly 30 years old!) design paradigm that is coding in Verilog/VHDL/SystemVerilog. :-)

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The practical reality of designing with FPGAs is that you are "stuck" with using whatever language that the vendor supports. I first selected VHDL because MAX+PLUS II did not support various Verilog constructs. I'm not an expert SystemVerilog user, but it appears to have lots of modern object-oriented constructs ... alas, I see various threads on things that work in Modelsim, but do not work in Quartus.

By all means play with MyHDL, and run the designs through Quartus, there are lots of happy users of the tools. However, once you have spent the time learning an HDL language (ancient though they may be), you'll find that there's really no advantage in using MyHDL over performing similar language tricks in an HDL language.

Cheers,

Dave