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Altera_Forum's avatar
Altera_Forum
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12 years ago

Python and VHDL

Hi every body I have a component in VHDL and I wanna making several copy of it and creating a Mesh M*N dimensions with them, if I will define whole the signals between them its take a long time...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

MyHDL just produces VHDL or Verilog.

In my experience, all tools that auto-generate HDL for you tend to be rubbish.

PS. System Verilog was only standardised in 2005.