Python and VHDL

Here's what I think is an interesting question; lets say you are a knowledgeable VHDL or Verilog engineer, and you've decided you really need to get a better handle on test and verification. As I see it you have several options;

1. VHDL; Use Jim Lewis' Open Source VHDL Verification Methodology (OS-VVM)

http://osvvm.org/

2. SystemVerilog; Use OVM (old) or UVM (new), eg., using Mentor Graphics extensive materials at the Verification Academy

https://verificationacademy.com/

Doulos has a nice UVM overview:

http://www.doulos.com/knowhow/sysverilog/uvm/

3. MyHDL

Taking a conservative view; (1) and (3) are "projects" created by very talented individuals, but "individuals" none-the-less. If I had to consider long-term support and longevity, then SystemVerilog (2) would be the obvious choice (at least for me).

If I had time, I'd be interested in checking out all three options, but the reality is I do not, so I'll continue coding in VHDL, and reading SystemVerilog verification books to learn more :)

Keep up the interesting discussion ... :)

Cheers,

Dave

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Very nice discussion.

I am all for HLS, and I am considering learning MyHDL.

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I missed this thread in February.

I have done a major project with MyHDL: classification using support vector machines (http://en.wikipedia.org/wiki/support_vector_machine) I had been looking to MyHDL for several years, but never got round to do more than a lazy Sunday afternoon's play-session. But this year my favourite customer actually 'required' to do this project in MyHDL. And it was great. Of course a lot of the RTL coding stays along the same lines (there is no magic silver HLS). But what impressed me most is the ease of generating self-checking testbenches. You have all the power of Python and the libraries to generate test-data and monitor the results. Making writing extensive testbenches a lot less tedious.

MyHDL produces perfect VHDL (I haven't checked the Verilog code, as I wouldn't touch that even with a bargepole) not being rubbish as claimed by Tricky.

Learning Python is about the best thing any engineer can do. Apart from MyHDL I have used Python to write an Assembler for a specialised CPU, generated pdf documentation (using pyx and psfile), and even designed some 3D objects with it (SolidPython -> OpenScad).

Now there is still a lot of room for improvement for MyHDL and the developers are working on nice futures like fixed point and interfaces. There are a few touchy points as well. MyHDL treats Verilog and VHDL code generation equally, which is a limitation e.g. in VHDL you can do double (and triple and ...) arrays which Verilog doesn't. As Dave mentions including an external IP core is also not straightforward as you to need to write a Python model for it. But you don't need to do everything in one language, do you?

So by all means, try it out.

If you need a little help or have a question, pop over to http://news.gmane.org/gmane.comp.python.myhdl

A hint: use the pydev (http://pydev.org), sigasi (http://www.sigasi.com/) and impulse (http://toem.de/index.php/projects/impulse) plugins in eclipse (http://www.eclipse.org/) and you'll 'have done 500 miles today and even never left la'

Hi Josy,

Thanks for providing your positive impression of MyHDL.

At the last couple of Embedded Systems Conferences in San Jose, I chatted with Chris Felton who has also implemented major projects in MyHDL. Googling his name comes up with a few MyHDL tutorials that people can look at;

http://www.xess.com/blog/learn-fpga-programming-with-myhdl/

https://bitbucket.org/cfelton/pyohio

http://www.fpgarelated.com/showarticle/25.php

https://bitbucket.org/cfelton/

Cheers,

Dave

Thanks Josy and Dave.

Going to try out MyHDL right now.

Cheers

So, I've have had some free time and decided to try out MyHDL. I am trying to re-write an ugly old module that I made 4 years ago when I was starting VHDL but I am struggling with synthesis.

It's working perfectly in Python! Here is my Py cordic code: http://pastebin.com/nzphemry and here is my testbench in Py: http://pastebin.com/ptqkwjn6

I do have a problem with the angle validation, The py function returns from -pi to pi and I have to do the same with my cordic, but I won't worry about that now.

So, I've generated the VHDL and compiled in my project, here is the VHDL: http://pastebin.com/5j5muvgq

Compared to my OLD VHDL ( http://pastebin.com/v9fjvuxr ), I do prefer the generated one, it uses less logic, the ports are smaller and it's also 1 uS faster (and I have python functions, yay). This OLD VHDL is really old, there are a few errors with it like mixing numeric_std and signed_artih, but...

the MyHDL VHDL isn't working in my product! :(

I know that's a lot of work, but I've been scratching my head and I can't find why the MyHDL VHDL isn't working. I am getting some random values from my acquisition board instead of the right mag/ang pair.

I've made a test bench with both VHDLs running in paralalel and I get the same result from both.

I don't know if it's a problem with the Variable usage or these cases returning a constant to a variable, or even the state machine being half if/else half case. Everything seems OK, I took a look at the RTL Viewer and didn't see anything strange.

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So, I've have had some free time and decided to try out MyHDL. I am trying to re-write an ugly old module that I made 4 years ago when I was starting VHDL but I am struggling with synthesis.

It's working perfectly in Python! Here is my Py cordic code: http://pastebin.com/nzphemry and here is my testbench in Py: http://pastebin.com/ptqkwjn6

I do have a problem with the angle validation, The py function returns from -pi to pi and I have to do the same with my cordic, but I won't worry about that now.

So, I've generated the VHDL and compiled in my project, here is the VHDL: http://pastebin.com/5j5muvgq

Compared to my OLD VHDL ( http://pastebin.com/v9fjvuxr ), I do prefer the generated one, it uses less logic, the ports are smaller and it's also 1 uS faster (and I have python functions, yay). This OLD VHDL is really old, there are a few errors with it like mixing numeric_std and signed_artih, but...

the MyHDL VHDL isn't working in my product! :(

I know that's a lot of work, but I've been scratching my head and I can't find why the MyHDL VHDL isn't working. I am getting some random values from my acquisition board instead of the right mag/ang pair.

I've made a test bench with both VHDLs running in paralalel and I get the same result from both.

I don't know if it's a problem with the Variable usage or these cases returning a constant to a variable, or even the state machine being half if/else half case. Everything seems OK, I took a look at the RTL Viewer and didn't see anything strange.

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Hi Aprado,

I compiled your code too and as you say everything looks very much OK. If the code is not working in the 'real' FPGA you will have to use SignalTap to find the error ...

One observation: if your result has a precision of 16 bits you can limit the 'num_iteracao' to 16 as the 8 remaining iterations will add 0 to the result. You can also gain one clock per iteration by testing 'num_iteracao' in state CALC_CORDIC_2 and then transition to a single final state to update the output and generate the 'finish_cordic' pulse.

Thanks Josy, it was indeed working. I had a problem with other modules because this one got faster, lol

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Hi Aprado,

I compiled your code too and as you say everything looks very much OK. If the code is not working in the 'real' FPGA you will have to use SignalTap to find the error ...

One observation: if your result has a precision of 16 bits you can limit the 'num_iteracao' to 16 as the 8 remaining iterations will add 0 to the result. You can also gain one clock per iteration by testing 'num_iteracao' in state CALC_CORDIC_2 and then transition to a single final state to update the output and generate the 'finish_cordic' pulse.

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I also did a simple UART design with MyHDL. It works just fine: https://github.com/andrecp/myhdl_simple_uart

:)

Cheers