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Altera_Forum
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12 years ago

Python and VHDL

Hi every body I have a component in VHDL and I wanna making several copy of it and creating a Mesh M*N dimensions with them, if I will define whole the signals between them its take a long time...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Thanks Josy, it was indeed working. I had a problem with other modules because this one got faster, lol

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Hi Aprado,

I compiled your code too and as you say everything looks very much OK. If the code is not working in the 'real' FPGA you will have to use SignalTap to find the error ...

One observation: if your result has a precision of 16 bits you can limit the 'num_iteracao' to 16 as the 8 remaining iterations will add 0 to the result. You can also gain one clock per iteration by testing 'num_iteracao' in state CALC_CORDIC_2 and then transition to a single final state to update the output and generate the 'finish_cordic' pulse.

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