Python and VHDL

So, I've have had some free time and decided to try out MyHDL. I am trying to re-write an ugly old module that I made 4 years ago when I was starting VHDL but I am struggling with synthesis.

It's working perfectly in Python! Here is my Py cordic code: http://pastebin.com/nzphemry and here is my testbench in Py: http://pastebin.com/ptqkwjn6

I do have a problem with the angle validation, The py function returns from -pi to pi and I have to do the same with my cordic, but I won't worry about that now.

So, I've generated the VHDL and compiled in my project, here is the VHDL: http://pastebin.com/5j5muvgq

Compared to my OLD VHDL ( http://pastebin.com/v9fjvuxr ), I do prefer the generated one, it uses less logic, the ports are smaller and it's also 1 uS faster (and I have python functions, yay). This OLD VHDL is really old, there are a few errors with it like mixing numeric_std and signed_artih, but...

the MyHDL VHDL isn't working in my product! :(

I know that's a lot of work, but I've been scratching my head and I can't find why the MyHDL VHDL isn't working. I am getting some random values from my acquisition board instead of the right mag/ang pair.

I've made a test bench with both VHDLs running in paralalel and I get the same result from both.

I don't know if it's a problem with the Variable usage or these cases returning a constant to a variable, or even the state machine being half if/else half case. Everything seems OK, I took a look at the RTL Viewer and didn't see anything strange.