Python and VHDL

Here's what I think is an interesting question; lets say you are a knowledgeable VHDL or Verilog engineer, and you've decided you really need to get a better handle on test and verification. As I see it you have several options;

1. VHDL; Use Jim Lewis' Open Source VHDL Verification Methodology (OS-VVM)

http://osvvm.org/

2. SystemVerilog; Use OVM (old) or UVM (new), eg., using Mentor Graphics extensive materials at the Verification Academy

https://verificationacademy.com/

Doulos has a nice UVM overview:

http://www.doulos.com/knowhow/sysverilog/uvm/

3. MyHDL

Taking a conservative view; (1) and (3) are "projects" created by very talented individuals, but "individuals" none-the-less. If I had to consider long-term support and longevity, then SystemVerilog (2) would be the obvious choice (at least for me).

If I had time, I'd be interested in checking out all three options, but the reality is I do not, so I'll continue coding in VHDL, and reading SystemVerilog verification books to learn more :)

Keep up the interesting discussion ... :)

Cheers,

Dave