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Altera_Forum
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12 years ago

Python and VHDL

Hi every body I have a component in VHDL and I wanna making several copy of it and creating a Mesh M*N dimensions with them, if I will define whole the signals between them its take a long time...
Altera_Forum's avatar
Altera_Forum
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11 years ago

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So, I've have had some free time and decided to try out MyHDL. I am trying to re-write an ugly old module that I made 4 years ago when I was starting VHDL but I am struggling with synthesis.

It's working perfectly in Python! Here is my Py cordic code: http://pastebin.com/nzphemry and here is my testbench in Py: http://pastebin.com/ptqkwjn6

I do have a problem with the angle validation, The py function returns from -pi to pi and I have to do the same with my cordic, but I won't worry about that now.

So, I've generated the VHDL and compiled in my project, here is the VHDL: http://pastebin.com/5j5muvgq

Compared to my OLD VHDL ( http://pastebin.com/v9fjvuxr ), I do prefer the generated one, it uses less logic, the ports are smaller and it's also 1 uS faster (and I have python functions, yay). This OLD VHDL is really old, there are a few errors with it like mixing numeric_std and signed_artih, but...

the MyHDL VHDL isn't working in my product! :(

I know that's a lot of work, but I've been scratching my head and I can't find why the MyHDL VHDL isn't working. I am getting some random values from my acquisition board instead of the right mag/ang pair.

I've made a test bench with both VHDLs running in paralalel and I get the same result from both.

I don't know if it's a problem with the Variable usage or these cases returning a constant to a variable, or even the state machine being half if/else half case. Everything seems OK, I took a look at the RTL Viewer and didn't see anything strange.

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Hi Aprado,

I compiled your code too and as you say everything looks very much OK. If the code is not working in the 'real' FPGA you will have to use SignalTap to find the error ...

One observation: if your result has a precision of 16 bits you can limit the 'num_iteracao' to 16 as the 8 remaining iterations will add 0 to the result. You can also gain one clock per iteration by testing 'num_iteracao' in state CALC_CORDIC_2 and then transition to a single final state to update the output and generate the 'finish_cordic' pulse.