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Altera_Forum's avatar
Altera_Forum
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17 years ago

Protect name of an entity pin

Moi

I have the following problem: An output of an entity is directly fed by a state machine. After mapping, this signal is called something like Mux324, having a different number after hdl changes. I now want to put an assignment on this signal...

I could not find a way to protect the name of the signal so far. It is the output of a Mux, not a register, so PRESERVE_REGISTER doesn't work. PROTECT_HIERARCHICAL_BOUNDARY doesn't help either, the name is changed. IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL produces nothing new, the signal is already an lcell-output. LCELL_INSERTION doesn't work on StratixIII (correct?)

I have some far-a-way memories, that there was some assignment to protect logic, but I can't find that one anymore (would it help?)

Any ideas?

Thanks

emanuel

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    VHDL? Are you using Quartus for Synthesis? I assume so since you said entity. Open the VHDL file in Quartus II, go to Edit -> Insert Template -> VHDL -> Synthesis Attributes and look at Using Synthesis Attributes and the Keep attribute. Basically you want to assign a keep attribute to that net. (Out of curiosity, why do you need to keep that net? Things generally work much easier when you accept combinatorial nodes get synthesized and renamed. I'm not saying there aren't times, as I'm working on a clock mux that requires this, but in general it's best to avoid...)

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Jep, VHDL, but I would prefer not to mess with the HDL ;)

    Similar problem as for the last one you were helping me ;): The HDL is targeted for the ASIC. The signal I'd like to work on is the scan clock output from the test cell. As this is a) not functional anyway on the FPGA (no scan chain...) and b) messes with the timing, I'd like to define a SCAN_CLK and ignore this one completely. I cannot ignore the TCK input, because we still need the JTAG to the ARM...

    To be able to define a SCAN_CLK, I need the source - which is this mux with the not constant name.

    So: If I start to make a HDL diversion between the FPGA and the ASIC, I can as well just cut the signal. Nice would be to have no diversion.

    Ahh, right: The decision, that the scan clock origins from a state machine mux, is not mine...
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    So your case is a perfect example for doing this type of thing. I have made clock assignments to muxes in the past, and don't remember the name changing, but it's a little funny. You could try the "Implement as Output of Logic Cell", and I think that should work. Probably worth making a test case though.

    Also, you could make your assignment a little more generic if the name changes, i.e. when applying the clock constraint, apply it to something like [get_pins mux*]. That won't be the exact syntax, but play with the Name Finder in TimeQuest to get it right.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I think I tried "Implement as output of logic cell". The problem is, that it is already a logic cell, and the manual states that it won't insert an additional lcell, if there is already one. At least I didn't see any change.

    A more generic name definitely helps, yes. But there are many muxes in that cell, so I would have to put them all into the constraint (I can't distinguish them). I have no idea what this produces, maybe I should try ;) But I'm a bit afraid that this either produces an error (now that's an easy one to try) or ignores connections it shouldn't (this one rather less).

    Maybe I should just figure out, why the name changes...
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Just for the records:

    I checked this one with the altera support, as the "Implement as output of logic cell" didn't work. So the answer is (In my own words):

    "Implement as output of logic cell" and the VHDL "Keep" attribute are the same - nearly. There is small difference:

    * "Keep" is already accounted for in the very beginning of the Analysis & Elaboration stage.

    * "Implement as output of logic cell" is only considered in the Synthesis stage.

    This makes exactly the difference I see: The output name of a state machine is kept with the "keep"-attribute but not with the logic option.

    /Emanuel
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Just for the records:

    I checked this one with the altera support, as the "Implement as output of logic cell" didn't work. So the answer is (In my own words):

    "Implement as output of logic cell" and the VHDL "Keep" attribute are the same - nearly. There is small difference:

    * "Keep" is already accounted for in the very beginning of the Analysis & Elaboration stage.

    * "Implement as output of logic cell" is only considered in the Synthesis stage.

    This makes exactly the difference I see: The output name of a state machine is kept with the "keep"-attribute but not with the logic option.

    /Emanuel

    --- Quote End ---

    Hi,

    I'm facing the same issue but I do not want to use the keep attribute to avoid buffer insertion.

    Is there any other way to preserve nodes/pins in the final netlist to set timign constraint ?

    Alex.