Protect name of an entity pin

VHDL? Are you using Quartus for Synthesis? I assume so since you said entity. Open the VHDL file in Quartus II, go to Edit -> Insert Template -> VHDL -> Synthesis Attributes and look at Using Synthesis Attributes and the Keep attribute. Basically you want to assign a keep attribute to that net. (Out of curiosity, why do you need to keep that net? Things generally work much easier when you accept combinatorial nodes get synthesized and renamed. I'm not saying there aren't times, as I'm working on a clock mux that requires this, but in general it's best to avoid...)