Protect name of an entity pin

Jep, VHDL, but I would prefer not to mess with the HDL ;)

Similar problem as for the last one you were helping me ;): The HDL is targeted for the ASIC. The signal I'd like to work on is the scan clock output from the test cell. As this is a) not functional anyway on the FPGA (no scan chain...) and b) messes with the timing, I'd like to define a SCAN_CLK and ignore this one completely. I cannot ignore the TCK input, because we still need the JTAG to the ARM...

To be able to define a SCAN_CLK, I need the source - which is this mux with the not constant name.

So: If I start to make a HDL diversion between the FPGA and the ASIC, I can as well just cut the signal. Nice would be to have no diversion.

Ahh, right: The decision, that the scan clock origins from a state machine mux, is not mine...