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Just for the records:
I checked this one with the altera support, as the "Implement as output of logic cell" didn't work. So the answer is (In my own words):
"Implement as output of logic cell" and the VHDL "Keep" attribute are the same - nearly. There is small difference:
* "Keep" is already accounted for in the very beginning of the Analysis & Elaboration stage.
* "Implement as output of logic cell" is only considered in the Synthesis stage.
This makes exactly the difference I see: The output name of a state machine is kept with the "keep"-attribute but not with the logic option.
/Emanuel
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Hi,
I'm facing the same issue but I do not want to use the keep attribute to avoid buffer insertion.
Is there any other way to preserve nodes/pins in the final netlist to set timign constraint ?
Alex.
Honored Contributor
