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Altera_Forum's avatar
Altera_Forum
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13 years ago

Proper Use Of SOPC Builder Exports

Using Quartus 2/SOPC Builder/Compnent Builder to develop application on TerASIC DE2-115

Have developed two custom components. Component 1 contains an single bit export (output) that is connected to a D2 GPIO pin. This part works fine. Component 2 contains a single bit export (input) that I would like to tie to component 1's output.

In my top level file I have:

.output_from_the_component1 (GPIO[0])

.input_to_the_component1(.output_from_the_component1);

When I compile, I get a "can't declare implicit net "output_from_the_compenet1" because the current value of default_nettype is none." This seems to imply that the net output_from_the_compenet1 isn't visible from the top level module although it is recognized in the first statement.

Not sure I quite understand the syntax containing the period completely.l Would appreciate a little insight. Also, is the export mechanism the "best way" to make this connection (If so, guidance on the proper syntax would be appreciated). If not, what is the better way.

Thanks in advance,

ME

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    btw,, the period in front of output_from_the_compenet1 in the second assignment is a typo. It shouldn't be there. If I use the period, I get a syntax error on the Period.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I'm not sure how it works in verilog, but in VHDL you would make an intermediate signal that would go to the input and output. Then you would map this signal to the GPIO.

    For example:

    wire test_signal;

    .output_from_the_component1 (test_signal)

    .input_to_the_component1(test_signal);

    assign GPIO[0] = test_sginal;
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thnx rawbus..

    I dorked around with that as well. I think the problem is I don't completely understand the notation (and can't find any documentation on it) In this case:

    .output_from_the_component1 (GPIO[0]), the implication is that output_from_the_component is wired to GPIO[0] (Pretty sure this is correct as I can see the proper activity on GPIO[0] with a scope).

    I also can see the input_to_the_component2 instance in the SOPC Builder output. What I haven't been able to figure out is how to wire these together at the top level.

    Am still pretty new to Verilog/VHDL/etc. So still trying to get the paradigm straight in my head.

    Thnx again,

    ME
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hey rawbus. Thnx again. Using you example I was able to get it to work. Newbie question though. Other than syntax, why the need for the intermediate signal. Seems I should be able to directly wire the two together....

    thnx again,

    ME
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I've not seen the convention of putting a port instantiation such as .output_from_the_component1 as an input to another port(with or without the dot). I can't really give you a language definition reason, other than it doesn't work that way. They generally have to be either wires, or signals from the top level.

    In verilog I believe you can use implicit signals as well where you don't declare them ahead of time, but again they aren't port declarations.

    The only comparison I can give you is think of the .XXX names as the nodes and the (YYY) as the paths. You can't assign another node as a path. There is probably a more accurate comparison but that should help you some what.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Your last sentence cleared the fog from my feeble little brain. I guess if you look at it from a "real" set of components, I can't directly connect a pin on 1 chip to a pin on a second chip. I need a wire. Seems the same applies here (and rightfully so)...

    Thnx much...

    ME