Forum Discussion
Altera_Forum
Honored Contributor
13 years agoThnx rawbus..
I dorked around with that as well. I think the problem is I don't completely understand the notation (and can't find any documentation on it) In this case: .output_from_the_component1 (GPIO[0]), the implication is that output_from_the_component is wired to GPIO[0] (Pretty sure this is correct as I can see the proper activity on GPIO[0] with a scope). I also can see the input_to_the_component2 instance in the SOPC Builder output. What I haven't been able to figure out is how to wire these together at the top level. Am still pretty new to Verilog/VHDL/etc. So still trying to get the paradigm straight in my head. Thnx again, ME