Proper Use Of SOPC Builder Exports

I've not seen the convention of putting a port instantiation such as .output_from_the_component1 as an input to another port(with or without the dot). I can't really give you a language definition reason, other than it doesn't work that way. They generally have to be either wires, or signals from the top level.

In verilog I believe you can use implicit signals as well where you don't declare them ahead of time, but again they aren't port declarations.

The only comparison I can give you is think of the .XXX names as the nodes and the (YYY) as the paths. You can't assign another node as a path. There is probably a more accurate comparison but that should help you some what.