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Altera_Forum
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13 years ago

Proper Use Of SOPC Builder Exports

Using Quartus 2/SOPC Builder/Compnent Builder to develop application on TerASIC DE2-115 Have developed two custom components. Component 1 contains an single bit export (output) that is connec...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I'm not sure how it works in verilog, but in VHDL you would make an intermediate signal that would go to the input and output. Then you would map this signal to the GPIO.

For example:

wire test_signal;

.output_from_the_component1 (test_signal)

.input_to_the_component1(test_signal);

assign GPIO[0] = test_sginal;