Dear my best friends I used vhdl to calculate SVPWM algorithm. I used LPM library for divider. I'd already initial value for all of signal, but It still has "X" value. This is LPM library m0 : lpm_divide----------divide component GENERIC MAP (LPM_WIDTHN=>32, LPM_WIDTHD =>32, LPM_PIPELINE=>1,LPM_NREPRESENTATION =>"SIGNED", LPM_DREPRESENTATION =>"SIGNED") port map (numer=>A,denom=>B,clock=>clk_120n,quotient=>sat); these are initial value: signal TTA,TTB,T_sum : STD_LOGIC_VECTOR(31 downto 0):=(others =>'0'); signal A,B,sat : STD_LOGIC_VECTOR(31 downto 0):=(others =>'0'); signal T1,T2 : STD_LOGIC_VECTOR(15 downto 0):=(others =>'0'); signal TAA,TBB : STD_LOGIC_VECTOR(15 downto 0):=(others =>'0'); these are my code: if clk_120n'event and clk_120n='1' then CNT<=CNT+1; if CNT=x"00" then SECT <= not (Vref3(11) & Vref2(11) & Vref1(11) ); elsif CNT=x"01" then TX<=Vref1; TY<=-Vref2; TZ<=-Vref3; ELSIF CNT=x"02" THEN case SECT is when "011" => T1 <= -TZ; T2 <= TX; when "001" => T1 <= TZ; T2 <= TY; when others => T1 <= T1; T2 <= T2; end case; elsif CNT=x"03" then T_sum <=x"0000"& (T1+T2); if T_sum>= x"410" then --X"410" TTA <=T1*x"0410"; TTB <=T2*x"0410"; else TAA <=T1; TBB <=T2; end if; elsif CNT=x"04" then if T_sum>=x"410" then A <=TTA; B <=T_sum; end if; elsif CNT=x"05" then if T_sum>=x"410" then TAA <= sat(15 downto 0); end if; elsif CNT=x"06" then if T_sum>=x"410" then A <=TTB; B <=T_sum; end if; elsif CNT=x"07" then if T_sum>=x"410" then TBB <= sat (15 downto 0); end if; elsif CNT=x"08" then TAM <= x"410" -TAA -TBB; elsif CNT=x"09" then TAO <= '0' & TAM(15 downto 1); elsif CNT=x"0A" then TBO <= TAO + TAA; elsif CNT=x"0B" then TCO <= TBO + TBB; end if; end if; The value get "X" value is SAT (result of divider command). I attached the waveforms in this message. I spent a lot of time for it but I still had not found the error. Please could you help me? Thank you very much.

X output is usually the result of trying to drive 1 bus from two sources, or you put an invalid value (like 'X' or 'U) into the multiplier. The error will be with the source data.

I don't understand, why you posted all the code above. the input to the divider, that must be expected to cause the 'U' in various other signals is missing in the code. So it can't be seen, where A and B are assigned.

The input of divider is A and B. A and B were signed value from this code: if T_sum>=x"410" then A <=TTA; B <=T_sum; end if; AND: if T_sum>=x"410" then A <=TTB; B <=T_sum; end if; Where TTA and TTB were signed value from: if T_sum>= x"410" then --X"410" TTA <=T1*x"0410"; TTB <=T2*x"0410"; else TAA <=T1; TBB <=T2; end if; T1 and T2 were signed value from Tx, Ty, Tz. when "011" => T1 <= -TZ; T2 <= TX; when "001" => T1 <= TZ; T2 <= TY; when "101" => T1 <= TX; T2 <= -TY; in this case, Tx, Ty, Tz were signed value from Vref1, Vref2, Vref3 with Vref1, Vref2, Vref3 were read from memory initialization file (I attached the waveforms of Vref1, Vref2, Vref3 in this message. In my opinion, All value are real values. I don't know why the result of SAT has "X". I really don't understand this. Thank you very much.

Did you reset A and B to some constant? because in your above code they only get set on specific paths.

I had signed all signal with initial value but the result of SAT still get "X" signal TTA,TTB,T_sum : STD_LOGIC_VECTOR(31 downto 0):=(others =>'0'); signal A,B,sat : STD_LOGIC_VECTOR(31 downto 0):=(others =>'0'); signal T1,T2 : STD_LOGIC_VECTOR(15 downto 0):=(others =>'0'); signal TAA,TBB : STD_LOGIC_VECTOR(15 downto 0):=(others =>'0'); signal TX,TY,TZ : STD_LOGIC_VECTOR(15 downto 0):=(others =>'0'); signal TAM : STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');

Altera_Forum

Honored Contributor

15 years ago

problem with value 'X' in VHDL

Dear my best friends

I used vhdl to calculate SVPWM algorithm. I used LPM library for divider. I'd already initial value for all of signal, but It still has "X" value.

This is LPM library

m0 : lpm_divide----------divide component
GENERIC MAP (LPM_WIDTHN=>32, LPM_WIDTHD =>32, LPM_PIPELINE=>1,LPM_NREPRESENTATION =>"SIGNED", LPM_DREPRESENTATION =>"SIGNED")
port map (numer=>A,denom=>B,clock=>clk_120n,quotient=>sat);

these are initial value:

signal TTA,TTB,T_sum	: STD_LOGIC_VECTOR(31 downto 0):=(others =>'0');
signal A,B,sat			: STD_LOGIC_VECTOR(31 downto 0):=(others =>'0');
signal T1,T2			: STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');
signal TAA,TBB          : STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');

these are my code:

if clk_120n'event and clk_120n='1' then
	CNT<=CNT+1;
if CNT=x"00" then 
	SECT  <= not (Vref3(11) & Vref2(11) & Vref1(11) );
elsif CNT=x"01" then
	TX<=Vref1;
	TY<=-Vref2;
	TZ<=-Vref3;
ELSIF CNT=x"02" THEN
case SECT is
when "011" =>    
	T1  <=  -TZ;
	T2  <=  TX;
when "001" =>    
	T1  <=  TZ;
	T2  <=  TY;
when others =>
	T1  <=  T1;  
	T2  <=  T2;  
end case;
elsif CNT=x"03" then
	T_sum <=x"0000"& (T1+T2); 
	if T_sum>= x"410" then --X"410"      
		TTA <=T1*x"0410";
		TTB <=T2*x"0410";
	else
		TAA <=T1;
		TBB <=T2;
	end if;
elsif CNT=x"04" then 
	if T_sum>=x"410" then        
		A <=TTA;
		B <=T_sum;
	end if;   
elsif CNT=x"05" then
	if T_sum>=x"410" then 
		TAA <= sat(15 downto 0);
	end if;   
elsif CNT=x"06" then
	if T_sum>=x"410" then 
		A <=TTB;
		B <=T_sum;
	end if;   
elsif CNT=x"07" then
	if T_sum>=x"410" then 
		TBB <= sat (15 downto 0);
	end if;   
elsif CNT=x"08" then
	TAM  <= x"410" -TAA -TBB;    
elsif CNT=x"09" then
	TAO  <= '0' & TAM(15 downto 1);  
elsif CNT=x"0A" then
	TBO  <= TAO + TAA;
elsif CNT=x"0B" then
	TCO  <= TBO + TBB;        
end if;
end if;

The value get "X" value is SAT (result of divider command). I attached the waveforms in this message. I spent a lot of time for it but I still had not found the error.

Please could you help me?

Thank you very much.

23 Replies

Altera_Forum
Honored Contributor
15 years ago
X output is usually the result of trying to drive 1 bus from two sources, or you put an invalid value (like 'X' or 'U) into the multiplier. The error will be with the source data.
Altera_Forum
Honored Contributor
15 years ago
I don't understand, why you posted all the code above. the input to the divider, that must be expected to cause the 'U' in various other signals is missing in the code. So it can't be seen, where A and B are assigned.
Altera_Forum
Honored Contributor
15 years ago
The input of divider is A and B. A and B were signed value from this code:
if T_sum>=x"410" then A <=TTA; B <=T_sum; end if;

AND:
if T_sum>=x"410" then A <=TTB; B <=T_sum; end if;

Where TTA and TTB were signed value from:
if T_sum>= x"410" then --X"410" TTA <=T1*x"0410"; TTB <=T2*x"0410"; else TAA <=T1; TBB <=T2; end if;

T1 and T2 were signed value from Tx, Ty, Tz.
when "011" => T1 <= -TZ; T2 <= TX; when "001" => T1 <= TZ; T2 <= TY; when "101" => T1 <= TX; T2 <= -TY;

in this case, Tx, Ty, Tz were signed value from Vref1, Vref2, Vref3
with Vref1, Vref2, Vref3 were read from memory initialization file (I attached the waveforms of Vref1, Vref2, Vref3 in this message.

In my opinion, All value are real values.
I don't know why the result of SAT has "X". I really don't understand this.
Thank you very much.
Altera_Forum
Honored Contributor
15 years ago
Did you reset A and B to some constant? because in your above code they only get set on specific paths.

Altera_Forum

Honored Contributor

15 years ago

I had signed all signal with initial value but the result of SAT still get "X"

signal TTA,TTB,T_sum	: STD_LOGIC_VECTOR(31 downto 0):=(others =>'0');
signal A,B,sat			: STD_LOGIC_VECTOR(31 downto 0):=(others =>'0');
signal T1,T2			: STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');
signal TAA,TBB          : STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');
signal TX,TY,TZ			: STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');
signal TAM				: STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');

Altera_Forum
Honored Contributor
15 years ago
In the first two snipset of code that you show:
if T_sum>=x"410" then A <=TTA; B <=T_sum; end if;
and
if T_sum>=x"410" then A <=TTB; B <=T_sum; end if;
If TTA abd TTB have different values, A is assigned an 'X' value.
This propagates to the output of the divider.

it seems that in your code you use the bad practice of having different sections of the code (different circuits) that drive a single signal (A).

Every signal has to be defined from a single circuit for a safe and readable circuit (code).

Hope it helps.
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
If TTA abd TTB have different values, A is assigned an 'X' value.
This propagates to the output of the divider.

it seems that in your code you use the bad practice of having different sections of the code (different circuits) that drive a single signal (A).

Every signal has to be defined from a single circuit for a safe and readable circuit (code).

Hope it helps.
--- Quote End ---

That is wrong. This is only the case if they are code snippets from two different processes. If it is the same process, the A just takes the last value assigned to it.
Altera_Forum
Honored Contributor
15 years ago
where does the "x" input come from?
Altera_Forum
Honored Contributor
15 years ago
Why not post you project so that we can simulate it?
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
That is wrong
--- Quote End ---
I would say "this is not always true".

However, even if in a single process (and from the above snipset we don't know if this is the case, but we KNOW that the simulation shows a problem)
it is a bad practice to assign a signal in that way.

What kind of circuit is that?
It assigns to A the value TTA when T_sum<=x410,
further, it assigns to A the value of TTB in the same condition.
I assume that, if in a single process, there must be another if/case statements that selects between the two. This is too complex IMHO.

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problem with value 'X' in VHDL

23 Replies

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