problem with value 'X' in VHDL

In the first two snipset of code that you show:

if T_sum>=x"410" then        
        A <=TTA;
        B <=T_sum;
    end if;

and

if T_sum>=x"410" then 
        A <=TTB;
        B <=T_sum;
    end if;

If TTA abd TTB have different values, A is assigned an 'X' value.

This propagates to the output of the divider.

it seems that in your code you use the bad practice of having different sections of the code (different circuits) that drive a single signal (A).

Every signal has to be defined from a single circuit for a safe and readable circuit (code).

Hope it helps.