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Altera_Forum
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15 years ago

problem with value 'X' in VHDL

Dear my best friends I used vhdl to calculate SVPWM algorithm. I used LPM library for divider. I'd already initial value for all of signal, but It still has "X" value. This is LPM library m0...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I had signed all signal with initial value but the result of SAT still get "X" 

signal TTA,TTB,T_sum	: STD_LOGIC_VECTOR(31 downto 0):=(others =>'0');
signal A,B,sat			: STD_LOGIC_VECTOR(31 downto 0):=(others =>'0');
signal T1,T2			: STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');
signal TAA,TBB          : STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');
signal TX,TY,TZ			: STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');
signal TAM				: STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');