problem with value 'X' in VHDL

The input of divider is A and B. A and B were signed value from this code:

	if T_sum>=x"410" then        
		A <=TTA;
		B <=T_sum;
	end if;   

AND:

	if T_sum>=x"410" then 
		A <=TTB;
		B <=T_sum;
	end if; 

Where TTA and TTB were signed value from:

	if T_sum>= x"410" then --X"410"      
		TTA <=T1*x"0410";
		TTB <=T2*x"0410";
	else
		TAA <=T1;
		TBB <=T2;
	end if;

T1 and T2 were signed value from Tx, Ty, Tz.

when "011" =>   
	T1  <=  -TZ;
	T2  <=  TX;
when "001" =>
	T1  <=  TZ;
	T2  <=  TY;
when "101" =>  
	T1  <=  TX;
	T2  <=  -TY;

in this case, Tx, Ty, Tz were signed value from Vref1, Vref2, Vref3

with Vref1, Vref2, Vref3 were read from memory initialization file (I attached the waveforms of Vref1, Vref2, Vref3 in this message.

In my opinion, All value are real values.

I don't know why the result of SAT has "X". I really don't understand this.

Thank you very much.