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Altera_Forum's avatar
Altera_Forum
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15 years ago

problem with value 'X' in VHDL

Dear my best friends I used vhdl to calculate SVPWM algorithm. I used LPM library for divider. I'd already initial value for all of signal, but It still has "X" value. This is LPM library m0...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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If TTA abd TTB have different values, A is assigned an 'X' value.

This propagates to the output of the divider.

it seems that in your code you use the bad practice of having different sections of the code (different circuits) that drive a single signal (A).

Every signal has to be defined from a single circuit for a safe and readable circuit (code).

Hope it helps.

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That is wrong. This is only the case if they are code snippets from two different processes. If it is the same process, the A just takes the last value assigned to it.