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Altera_Forum's avatar
Altera_Forum
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17 years ago

Problem with Ports in Verilog and Quartus II

First off, I am a newbie and am probably doing something dumb, but I am getting frustrated that I can't figure out what's wrong. I am using Verilog and Quartus II, ver 8.

I am working on a design and the ports are not reading correctly. I searched the web and found the following design example from Altera and it is doing the same thing. BTW I reduced the bus widths to 3 from 8 in the original.

http://www.altera.com/support/examples/verilog/ver_bidirec.html

module bidir (oe, clk, inp, outp, bidir);

input oe;

input clk;

input [2:0] inp;

output [2:0] outp;

inout [2:0] bidir;

reg [2:0] a;

reg [2:0] b;

assign bidir = oe ? a : 3'bZ ;

assign outp = b;

always @ (posedge clk)

begin

b <= bidir;

a <= inp;

end

endmodule

Everything compiles and seems to simulate correctly, except the outputs are not what I expect.

  1. "bidir" - always high-z

  2. "bidir results" - looks like what I expect on "bidir"

  3. "outp" - is high-z for some of the time of simulation
Here is a screen shot of the simulation output:

https://www.alteraforum.com/forum/attachment.php?attachmentid=720

Thank you in advance,

Steve

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    How about trying this variation: 

    module bidir (oe, clk, inp, outp, bidir);
input oe;
input clk;
input  inp;
output  outp;
inout  bidir;
reg  a;
wire  b;
 
assign bidir = oe ? a : 3'bZ ;
assign b = bidir;
assign outp = b;
 
always @ (posedge clk) a <= inp;
 
endmodule
    I tried this on my system and it worked.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You basically misinterpreted the results.

    The shown bidir and bidir.results are apparently the nodes inserted by the simulator automaticly. You should take the time to understand´their meaning before complaining about the wrong results.

    bidir in this case represents the simulator stimulus to the bidir pins. Cause you don't drive these pins at all, the value is correctly high-Z.

    bidir.results means the state driven to the bidir pins. It is shown correctly to my opinion.

    output pins are actually not showing high-Z, they show unknown state because of the open bidir pins, which is abolutely correct.

    @Viziee: You didn't tell which problem you wanted to address with your modifications. To my opinion, both codes show meaningful results. They are of course different.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    First of all, if it sounded like I was complaining about Quartus returning wrong results, I did not mean it that way. I figured I was doing something wrong or not understanding it correctly.

    vizziee - thanks. Except for the first clock cycle, your code does the same thing. Since it uses a continuous assign statement instead of synchronous, that makes sense to me.

    FvM - thanks for explaining. So if I understand it right...

    In the output file the "bidir" signal is the "input" part of the inout port and the "bidir_result" is the actual state of the pin if this were implemented in a physical design. is that right?

    And, since I am loading "bidir" into "b" and then "b" into "outp" it is unknown for the first half of the simulation time while "bidir" is high-z. correct?

    Thanks guys,

    Steve