Problem with Ports in Verilog and Quartus II

First of all, if it sounded like I was complaining about Quartus returning wrong results, I did not mean it that way. I figured I was doing something wrong or not understanding it correctly.

vizziee - thanks. Except for the first clock cycle, your code does the same thing. Since it uses a continuous assign statement instead of synchronous, that makes sense to me.

FvM - thanks for explaining. So if I understand it right...

In the output file the "bidir" signal is the "input" part of the inout port and the "bidir_result" is the actual state of the pin if this were implemented in a physical design. is that right?

And, since I am loading "bidir" into "b" and then "b" into "outp" it is unknown for the first half of the simulation time while "bidir" is high-z. correct?

Thanks guys,

Steve