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Altera_Forum
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17 years ago

Problem with Ports in Verilog and Quartus II

First off, I am a newbie and am probably doing something dumb, but I am getting frustrated that I can't figure out what's wrong. I am using Verilog and Quartus II, ver 8. I am working on a des...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

How about trying this variation: 

module bidir (oe, clk, inp, outp, bidir);
input oe;
input clk;
input  inp;
output  outp;
inout  bidir;
reg  a;
wire  b;
 
assign bidir = oe ? a : 3'bZ ;
assign b = bidir;
assign outp = b;
 
always @ (posedge clk) a <= inp;
 
endmodule
I tried this on my system and it worked.