Problem with Ports in Verilog and Quartus II

You basically misinterpreted the results.

The shown bidir and bidir.results are apparently the nodes inserted by the simulator automaticly. You should take the time to understand´their meaning before complaining about the wrong results.

bidir in this case represents the simulator stimulus to the bidir pins. Cause you don't drive these pins at all, the value is correctly high-Z.

bidir.results means the state driven to the bidir pins. It is shown correctly to my opinion.

output pins are actually not showing high-Z, they show unknown state because of the open bidir pins, which is abolutely correct.

@Viziee: You didn't tell which problem you wanted to address with your modifications. To my opinion, both codes show meaningful results. They are of course different.