Problem witch implementing big automaton

77250 states !! Wah !! :-)

"out of memory in module quartus_map.exe" --> change your computer

In Assignments->Settings->Compilation Process Settings->More settings...-> you can try "enable reduced memory mode"

Look at http://www.altera.com/support/kdb/solutions/rd11102009_495.html

and http://www.altera.com/support/kdb/solutions/rd10202009_168.html

You can try Logic partition (with subscription version of Quartus)

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Hi!

I have serious problem with implementing big automaton in VHDL (it has about 77250 states). When i try complie project in Quartus, everytime i get an error "Out of memory in module quartus_map.exe". Is someone can help me? I am thinking about changing state machine encoding but i don't have too much experience- i don't know witch encoding standard use and i don't know does the state encoding change can help?

I have also secound problem connected to encoding standards. I don't know where can i change encoding standards. In manuals i found information that it is in Assigments->Settings->Analysis & Synthesis Settings but in Quartus i use (version 9.1) there is nothing about states encoding.

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Hi,

regarding your second problem. When you are on the Analysis & Synthesis tab there

is a button "more settings". Somewhere at the end of the list is an entry called "statemachine processing".

Kind regards

GPK

OK. I had changed my computer into much faster (4GB RAM). I get the same error. I'm afraid my automaton is to big. Do you know any ways to efficient implement automaton in FPGA? My implementation looks:

process (state_reg, stream)

begin

found <= '0';

case state_reg is

when s0 =>

found <= '0';

if stream = "01010110" then

state_next <= s1;

fail_edge <= '0';

elsif stream = "01000011" then

state_next <= s21;

fail_edge <= '0';

elsif stream = "01000010" then

state_next <= s38;

fail_edge <= '0';

elsif stream = "00110001" then

state_next <= s61;

fail_edge <= '0';

elsif stream = "01001001" then

state_next <= s77;

fail_edge <= '0';

elsif stream = "01001000" then

state_next <= s104;

fail_edge <= '0';

elsif stream = "01110101" then

state_next <= s116;

fail_edge <= '0';

elsif stream = "00101010" then

state_next <= s127;

fail_edge <= '0';

elsif stream = "01001101" then

state_next <= s155;

fail_edge <= '0';

elsif stream = "00101000" then

state_next <= s172;

fail_edge <= '0';

elsif stream = "00001010" then

state_next <= s196;

fail_edge <= '0';

... etc etc

Do you know any more memory efficient way to implement such automaton. I will be glad for all answers.

Thanks in advance!

you will need a large number of the dear registers and logic. You better implement it in memory as lut. What actually you want to do? Sounds an overkill or beyond fpga boundaries.

alternatively use a counter.

Hi,

never tried to use such a huge FSM but...

Quartus is problably trying to use one hot encoding.

You can try and add the following, to have Quartus use a sequential encoding, which

attribute syn_encoding : string;

attribute syn_encoding of state_reg : type is "sequential";

That said.. 70k states? *wow*

It's hard to see what your application is but 70k states is .. a lot.

Probalbly, you should consider other aproaches.

Maybe a 8 bit embedded processor core would help you.

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You better implement it in memory as lut. What actually you want to do?

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Honestly I don't have hudge experience with FPGA. I found tutorial how to implement automatons using code as I wrote in earlier post. Do you know any tutorial where can i found information about implementing it in memory? (or if it isn't very complicated could you explain it for my)

About encoding states I was trying all encoding standards including Sequential. It doesn't help- everytime i get same error.

Thanks in advance for every advaice.

Greetings!

Let us implement manually the FSM in a counter that runs from 0 to 77250-1. A counter this size is no problem but the extra logic is phenomenal

signal count : integer range 0 to 77250 := 0;
 
--put defaults here
case count is
       when => 0  
            all your actions...
 
        when 1 => 
            all your actions....
 
        when 77250-1 =>
            all your actions

I still find it hard to write 77250 cases... surely you need extra tool to automate the code e.g. C or Matlab m file

if your state machine code example above is all you want to do then put the

fail_edge <= '0'; at top only as default and don't repeat it. then all you need is set the counter to required value:

when 0 => count <= 1

when 1 => count <= 23

and so on...

I'm not exacly understand how to use counter. Especially in process witch is responsible on changeing states. In last version I used something like this:

process (clk, rst)

begin

if (rst = '1') then

state_reg <= s0;

elsif rising_edge(clk) then

if divideclk = '1' then

state_reg <= state_next;

divideclk <= '0';

else

divideclk <= '1';

end if;

end if;

end process;

and in main process sensitivity list I had state_reg and stream. I'm not sure how to change it to use counter instead of state_reg and state_next?

Thanks in advance