Honored Contributor
Honored ContributorOK. I had changed my computer into much faster (4GB RAM). I get the same error. I'm afraid my automaton is to big. Do you know any ways to efficient implement automaton in FPGA? My implementation looks:
process (state_reg, stream) begin found <= '0'; case state_reg is when s0 => found <= '0'; if stream = "01010110" then state_next <= s1; fail_edge <= '0'; elsif stream = "01000011" then state_next <= s21; fail_edge <= '0'; elsif stream = "01000010" then state_next <= s38; fail_edge <= '0'; elsif stream = "00110001" then state_next <= s61; fail_edge <= '0'; elsif stream = "01001001" then state_next <= s77; fail_edge <= '0'; elsif stream = "01001000" then state_next <= s104; fail_edge <= '0'; elsif stream = "01110101" then state_next <= s116; fail_edge <= '0'; elsif stream = "00101010" then state_next <= s127; fail_edge <= '0'; elsif stream = "01001101" then state_next <= s155; fail_edge <= '0'; elsif stream = "00101000" then state_next <= s172; fail_edge <= '0'; elsif stream = "00001010" then state_next <= s196; fail_edge <= '0'; ... etc etc Do you know any more memory efficient way to implement such automaton. I will be glad for all answers. Thanks in advance!
