Altera_Forum
Honored Contributor
Honored Contributorproblem VHDL help in code please
problem solved thank you all
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Altera_Forum--- Quote Start ---
and know ? can you help more --- Quote End --- really impressive for a beginner.It looks ok to me. 1) you need to assign 0 and not '0' to S at reset. Moreover you better reset all nodes inside process like S otherwise you get latches. 2) you can insert the * and + assignments inside the mux else...as well but it should do 3) your last challenge is to truncate final result into S within the range 0f 8 bits. your current code means S may overflow as it will accumulate several values of A*B. I am sure you can do that. The easiest way is to convert it to std_logic_vector and chop off some bits and convert it back to integer. It will be an exercise of type conversion experience.library ieee; use ieee.std_logic_1164.all; entity MAC is port( rst : in std_logic; clk : in std_logic; M : in std_logic; A : in integer range 0 to 2**8-1; B : in integer range 0 to 2**8-1; s : out integer range 0 to 2**8-1 ); end entity MAC; -------------------------------------------------- architecture rtl of MAC is signal A_reg: integer range 0 to 2**8-1; signal B_reg: integer range 0 to 2**8-1; signal AB: integer range 0 to 2**8-1; signal old_S: integer range 0 to 2**8-1; begin mycore: process(rst,clk) begin if rst = '1' then s <= '0'; -- ***** but s is integer? don't know what to do elsif rising_edge(clk) then if M = '1' then A_reg <= 0 ; B_reg <= 0; AB_reg <= 0; old_S <= 0; else A_reg <= A; B_reg <= B; end if; AB <= A_reg * B_reg ; old_s <= old_s_reg + AB_reg; s <= old_s; end if; end process; end architecture rtl;- Altera_Forum--- Quote Start --- kaz can I have your email --- Quote End --- you can send via private message at top left of menu. notice also that you have syntax error at signal name of old_s_reg(should be old_s)
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I have to post more 4 reply in order to send a message :P
really do you think that code will work :D I am so happy to hear that the problem of overflow : in the question s is integer of 8 bit changing the type will change the question is it right and in order to do that I need more tutorials + thank you so mush and yes I am really a beginner in VHDL who have to solve more problems latter also - Altera_Forum--- Quote Start --- I have to post more 4 reply in order to send a message :P really do you think that code will work :D I am so happy to hear that the problem of overflow : in the question s is integer of 8 bit changing the type will change the question is it right and in order to do that I need more tutorials + thank you so mush and yes I am really a beginner in VHDL how have to solve more problems latter also --- Quote End --- It should work, yes but obviously you need to simulate it first before going to hardware. overflow issue: keep your code as it is. but name S as S_int then add a conversion assignment of integer S_int to S2 as std_logic_vector say of 20 bits (in fact depends how many samples you accumulate). If you expect to accumulate 16 samples then S2 will require 8+8+4 bits = 20 finally discard 12 LSBs from S2 and convert to integer S for output. or may want to discard MSBs(depends on your spec)
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how to convert this vhdl code to verilog,please help me...
signal state1:main1:=(x"38",x"06",x"01",x"0c",x"80"); - Altera_Forum
please delete this thread and thank you
- Altera_Forum--- Quote Start --- please delete this thread and thank you --- Quote End --- The thread will not be deleted, it will remain in case others are in need of similar help.
- Altera_Forum--- Quote Start --- how to convert this vhdl code to verilog,please help me... signal state1:main1:=(x"38",x"06",x"01",x"0c",x"80"); --- Quote End --- I suggest you start your own thread rather than trying to hijack someone else's
