Altera_Forum
Honored Contributor
Honored Contributorproblem VHDL help in code please
problem solved thank you all
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Altera_ForumHonored Contributor
Honored Contributorhow to convert this vhdl code to verilog,please help me...
signal state1:main1:=(x"38",x"06",x"01",x"0c",x"80");
