problem VHDL help in code please

--- Quote Start ---

I have to post more 4 reply in order to send a message :P

really do you think that code will work :D I am so happy to hear that

the problem of overflow : in the question s is integer of 8 bit changing the type will change the question is it right and in order to do that I need more tutorials

+ thank you so mush and yes I am really a beginner in VHDL how have to solve more problems latter also

--- Quote End ---

It should work, yes but obviously you need to simulate it first before going to hardware.

overflow issue: keep your code as it is. but name S as S_int then add a conversion assignment of integer S_int to S2 as std_logic_vector say of 20 bits (in fact depends how many samples you accumulate). If you expect to accumulate 16 samples then S2 will require 8+8+4 bits = 20

finally discard 12 LSBs from S2 and convert to integer S for output. or may want to discard MSBs(depends on your spec)