problem VHDL help in code please

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library ieee;
use ieee.std_logic_1164.all;
entity MAC is
port(
     rst   : in  std_logic;
     clk   : in  std_logic;
     M     : in  std_logic;
     A     : in  integer range 0 to 2**8-1;
     B     : in  integer range 0 to 2**8-1;
     s     : out integer range 0 to 2**8-1
     );
end entity MAC;
--------------------------------------------------
architecture rtl of MAC is 
signal A_reg: integer range 0 to 2**8-1;
signal B_reg: integer range 0 to 2**8-1;
signal AB: integer range 0 to 2**8-1;
signal old_S:  integer range 0 to 2**8-1;
begin
mycore: process(rst,clk)
begin
if rst = '1' then 
     s <= '0';               -- ***** but s is integer? don't know what to do
elsif rising_edge(clk) then 
    if M = '1' then
       A_reg <= 0 ;
       B_reg <= 0;
       AB_reg <= 0;
       old_S <= 0;
    else 
       A_reg <= A;
       B_reg <= B;
   
    end if;
    AB <= A_reg * B_reg ;          
    old_s <= old_s_reg + AB_reg;  
    s <= old_s;
end if;
end process;
end architecture rtl;

and know ? can you help more

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really impressive for a beginner.It looks ok to me.

1) you need to assign 0 and not '0' to S at reset. Moreover you better reset all nodes inside process like S otherwise you get latches.

2) you can insert the * and + assignments inside the mux else...as well but it should do

3) your last challenge is to truncate final result into S within the range 0f 8 bits. your current code means S may overflow as it will accumulate several values of A*B. I am sure you can do that. The easiest way is to convert it to std_logic_vector and chop off some bits and convert it back to integer. It will be an exercise of type conversion experience.