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Altera_Forum's avatar
Altera_Forum
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12 years ago

problem VHDL help in code please

problem solved thank you all

18 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hey Tricky

    Actually I am new to VHDL and I don't know where to start from.

    I would really appreciate your help

    the started code 

    library ieee;
use ieee.std_logic_114.all;
entity MAC is
port(
rst, clk: in std_logic;
A, B : in integer range 0 to 2**8-1;
M : in integer range 0 to 2**1-1;
s : out std_logic);
end entity MAC
--------------------------------------------------
architecture rtl of MAC is 
begin
mycore: process(rst,clk)
begin
if rst = '1' then 
--- what to do----
else if rising_edge(clk) then 
---------what to write ----------
else 
---------------
end process;
end architecture rtl;
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I would start with a VHDL tutorial, or a good textbook. We're not going to do the work for you. When you're stuck you can come back here with specific problems?

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    dear tricky

    I need to learn and I need this resources I really want to solve this and to learn as well so can you help me and please also don't close this thread I well put some code later to solve some errors

    can you give me some pdfs or some videos to learn ? thank you
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I agree with Tricky that doing the exercise from a scratch is not recommended Forum practice.

    as a general guide I will suggest this:

    your A input goes to a box(possibly register)then to mux then to mult then to register then mux then adder with feedback.

    1) Name nodes: A, A_reg, mult_result, mult_reseult_reg, accum_result ...(you may not need naming all)

    2) Every mux is equivalent to a conditional statement be it sequential or combinatorial

    3) For mult you may just use operator *

    4) For add use operator +

    5) For any register you may instantiate it but since you are after rtl description then any assignment to a signal inside clock edge puts a register at assignment result

    6) You will need to truncate the result (s) back to 8 bits
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    tomorrow I will put the code may you check it and correct it ???

    --- Quote End ---

    plenty of correct code but see my notes below: 

    
library ieee;
use ieee.std_logic_114.all;
*****************
typing error, should be 
     use ieee.std_logic_1164.all;
*****************
entity MAC is
port(
rst, clk: in std_logic;
A, B : in integer range 0 to 2**8-1;
M : in std_logic;
s : out  integer range 0 to 2**8-1);
end entity MAC;
***************
ok but I prefer this below for readability:
entity MAC is
port(
     rst   : in  std_logic;
     clk   : in  std_logic;
     M     : in  std_logic;
     A     : in  integer range 0 to 2**8-1;
     B     : in  integer range 0 to 2**8-1;
     s     : out integer range 0 to 2**8-1
     );
end entity;
***************
--------------------------------------------------
-- no need to repeat library statements
--library ieee;
--use ieee.std_logic_114.all;
architecture rtl of MAC is 
signal A_reg: integer range 0 to 2**8-1;
signal B_reg: integer range 0 to 2**8-1;
signal AB: integer range 0 to 2**8-1;
signal old_S:  integer range 0 to 2**8-1;
signal AB_reg: integer range 0 to 2**8-1;
signal old_S_reg: integer range 0 to 2**8-1;
begin
mycore: process(rst,clk)
begin
if rst = '1' then 
     s <= '0';               -- ***** but s is integer?
elsif rising_edge(clk) then 
    if M = '1' then
       A_reg <= 0 ;
       B_reg <= 0;
       AB_reg <= 0;
       old_S_reg <= 0;
    else 
       A_reg <= A;
       B_reg <= B;
       AB_reg <= AB;         -- you don't need this extra register       
       old_s_reg <= old_s;   -- you don't need this extra register
    end if;
    AB <= A_reg + B_reg ;          -- wrong, you have added before multiplication     
    old_s <= old_s_reg * AB_reg;   -- wrong, should multiply A_reg * B_reg then accumulate result
    s <= old_s;
end if;
end process;
end architecture rtl;