problem VHDL help in code please

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tomorrow I will put the code may you check it and correct it ???

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plenty of correct code but see my notes below:

library ieee;
use ieee.std_logic_114.all;
*****************
typing error, should be 
     use ieee.std_logic_1164.all;
*****************
entity MAC is
port(
rst, clk: in std_logic;
A, B : in integer range 0 to 2**8-1;
M : in std_logic;
s : out  integer range 0 to 2**8-1);
end entity MAC;
***************
ok but I prefer this below for readability:
entity MAC is
port(
     rst   : in  std_logic;
     clk   : in  std_logic;
     M     : in  std_logic;
     A     : in  integer range 0 to 2**8-1;
     B     : in  integer range 0 to 2**8-1;
     s     : out integer range 0 to 2**8-1
     );
end entity;
***************
--------------------------------------------------
-- no need to repeat library statements
--library ieee;
--use ieee.std_logic_114.all;
architecture rtl of MAC is 
signal A_reg: integer range 0 to 2**8-1;
signal B_reg: integer range 0 to 2**8-1;
signal AB: integer range 0 to 2**8-1;
signal old_S:  integer range 0 to 2**8-1;
signal AB_reg: integer range 0 to 2**8-1;
signal old_S_reg: integer range 0 to 2**8-1;
begin
mycore: process(rst,clk)
begin
if rst = '1' then 
     s <= '0';               -- ***** but s is integer?
elsif rising_edge(clk) then 
    if M = '1' then
       A_reg <= 0 ;
       B_reg <= 0;
       AB_reg <= 0;
       old_S_reg <= 0;
    else 
       A_reg <= A;
       B_reg <= B;
       AB_reg <= AB;         -- you don't need this extra register       
       old_s_reg <= old_s;   -- you don't need this extra register
    end if;
    AB <= A_reg + B_reg ;          -- wrong, you have added before multiplication     
    old_s <= old_s_reg * AB_reg;   -- wrong, should multiply A_reg * B_reg then accumulate result
    s <= old_s;
end if;
end process;
end architecture rtl;