problem VHDL help in code please

I agree with Tricky that doing the exercise from a scratch is not recommended Forum practice.

as a general guide I will suggest this:

your A input goes to a box(possibly register)then to mux then to mult then to register then mux then adder with feedback.

1) Name nodes: A, A_reg, mult_result, mult_reseult_reg, accum_result ...(you may not need naming all)

2) Every mux is equivalent to a conditional statement be it sequential or combinatorial

3) For mult you may just use operator *

4) For add use operator +

5) For any register you may instantiate it but since you are after rtl description then any assignment to a signal inside clock edge puts a register at assignment result

6) You will need to truncate the result (s) back to 8 bits