problem VHDL help in code please

Hey Tricky

Actually I am new to VHDL and I don't know where to start from.

I would really appreciate your help

the started code

library ieee;
use ieee.std_logic_114.all;
entity MAC is
port(
rst, clk: in std_logic;
A, B : in integer range 0 to 2**8-1;
M : in integer range 0 to 2**1-1;
s : out std_logic);
end entity MAC
--------------------------------------------------
architecture rtl of MAC is 
begin
mycore: process(rst,clk)
begin
if rst = '1' then 
--- what to do----
else if rising_edge(clk) then 
---------what to write ----------
else 
---------------
end process;
end architecture rtl;