New ContributorProblem in using 2 NIOS cores with 2 PLLs and clock sources
I am trying to run two NIOSII cores on an DE0-CV board. They are supposed to run two application and don't need to share any resource. I also need them to run with two different clock rates. This is my design:
***for some reason pictures are unavailable so I am attaching my project.
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module DE0_CV_SDRAM_Nios_Test(
///////// CLOCK2 /////////
input CLOCK2_50,
///////// CLOCK3 /////////
input CLOCK3_50,
///////// CLOCK4 /////////
inout CLOCK4_50,
///////// CLOCK /////////
input CLOCK_50,
///////// DRAM /////////
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
///////// GPIO /////////
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
///////// HEX0 /////////
output [6:0] HEX0,
///////// HEX1 /////////
output [6:0] HEX1,
///////// HEX2 /////////
output [6:0] HEX2,
///////// HEX3 /////////
output [6:0] HEX3,
///////// HEX4 /////////
output [6:0] HEX4,
///////// HEX5 /////////
output [6:0] HEX5,
///////// KEY /////////
input [3:0] KEY,
///////// LEDR /////////
output [9:0] LEDR,
///////// PS2 /////////
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
///////// RESET /////////
input RESET_N,
///////// SD /////////
output SD_CLK,
inout SD_CMD,
inout [3:0] SD_DATA,
///////// SW /////////
input [9:0] SW,
///////// VGA /////////
output [3:0] VGA_B,
output [3:0] VGA_G,
output VGA_HS,
output [3:0] VGA_R,
output VGA_VS
);
//=======================================================
// REG/WIRE declarations
//=======================================================
DE0_CV_QSYS u0(
.clk_1_clk(CLOCK_50), // clk.clk
.reset_1_reset_n(1'b1), // reset.reset_n
.clk_2_clk(CLOCK2_50), // clk.clk
.reset_2_reset_n(1'b0), // reset.reset_n
//.key_external_connection_export(KEY), // key_external_connection.export
//.key2_external_connection_export(KEY), // key_external_connection.export
//SDRAM
// .clk_sdram_clk(DRAM_CLK), // clk_sdram.clk
// .sdram_wire_addr(DRAM_ADDR), // sdram_wire.addr
// .sdram_wire_ba(DRAM_BA), // .ba
// .sdram_wire_cas_n(DRAM_CAS_N), // .cas_n
// .sdram_wire_cke(DRAM_CKE), // .cke
// .sdram_wire_cs_n(DRAM_CS_N), // .cs_n
// .sdram_wire_dq(DRAM_DQ), // .dq
// .sdram_wire_dqm({DRAM_UDQM,DRAM_LDQM}), // .dqm
// .sdram_wire_ras_n(DRAM_RAS_N), // .ras_n
// .sdram_wire_we_n(DRAM_WE_N) // .we_n
);
endmoduleWhen I compile this, it compiles correctly and I can program my board. I use NIOSII to start a HelloWold application. I can successfully run that on core1.
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However when I try to run it on core2 I get an error.
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Does anybody know what I am doing wrong? I feel there is something wrong with my use of PLLs and clocks sources. But I have no clue what can be wrong. It looked working when I had both processors connected to CLOCK_50 and no PLL.
