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anaza3's avatar
anaza3
Icon for New Contributor rankNew Contributor
6 years ago

Problem in using 2 NIOS cores with 2 PLLs and clock sources

I am trying to run two NIOSII cores on an DE0-CV board. They are supposed to run two application and don't need to share any resource. I also need them to run with two different clock rates. This is ...
anaza3's avatar
anaza3
Icon for New Contributor rankNew Contributor
6 years ago

Hi,

Thank you for the reply. I attached pictures previously but it doesn't show them. I am attaching my project again. The PLL is not shared. I used a PLL for each core. I also used different clock sources and clock pins for each PLL.

P.s. I know it is possible to use one PLL with two outputs but for the purpose of my research I need to use two different PLLs.

Thank you,

Alireza

AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Alireza,

I have used your design with DE1-Nano/ Atlas kit, With some modifications(On-chip memory and integer PLL). i was able to run the design successfully.

Attached the project

Kindly recompile the cores, top level design and check .

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand